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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-22002-1E
ASSP Communication Control
IEEE 1394 Bus Controller (for DVC) MB86615
s DESCRIPTION
The MB86615 is 1394 serial bus controller compatible with the IEEE 1394 "FireWire" standard (IEEE Standard 1394-1995). One built-in port plus a differential transceiver and comparator are provided to enable formation of networks in a 1394 cable environment. The MB86615 supports s100 data transfer speeds. By integrating the physical layer and link layer on one chip, The MB86615 is designed to reduce mounting area as well as power consumption. The MB86615 has an exclusive data port for isochronous transfer, provides automatic packetizing for sending and separation of header and data units at receiving, and is optimized for continuity of transfer processing. The MB86615 supports DVC AV/C protocols, and includes the necessary built-in automatic operations and CSR's for providing the necessary operations for DVC data transfer.
s FEATURES
* * * * * * * Compatible with IEEE 1394 high-performance serial bus standards Physical layer and link layer integrated on one chip 1 cable ports Supports s100 transfer speed (98.304 Mbit/sec) 3.3V single power supply operation Built-in PLL (for crystal oscillator) for internal clock signal generation Power saving modes 1) Forced sleep mode at instruction from MPU 2) Automatic sleep mode for non-connected ports * Header and data units automatically separated at receiving and automatic packetizing for sending * Supports cycle master functions (Continued)
s PACKAGES
100-pin plastic LQFP 120-pin plastic FBGA
(FPT-100P-M05)
(BGA-120P-M01)
MB86615
(Continued) * Built-in CSR's to provide isochronous resource manager functions * 32-bit CRC generation and check functions * General purpose port for asynchronous transfer and control (16-bit MPU/DMA common bus) * Exclusive built-in ports for isochronous transfer (8-bit bus) * Built-in CRS's and automatic processes to support DVC 1) Automatic separation of CIP headers at receiving, and automatic packetizing at sending. 2) Automatic generation and match detection of time stamp by FP signal. 3) DBC area automatic increment function 4) No-data packet sending and receiving 5) On-chip PCR (input/output 1 channel each) 6) Each CSR with automatic C&S lock processing and read processing * Compatible with 4-core cable * Packages: LQFP-100, FBGA-120
2
MB86615
s PIN ASSIGNMENTS
1. LQFP-100
100 MODE1
MODE0 TEST5 FP ICRCE IV ILWRE IDIR ICLK VDD VSS ID0 ID1 ID2 ID3 ID4 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
RESET 1 INT VDD VSS ALE D15 D14 D13 D12 D11 D10 D9 D8 VDD VSS D7 D6 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
84 83 82 81 80 79 78 77 76
ID5 ID6 ID7 TEST4 TEST3 VSS VDD TEST2 TEST1
75 AVDD 74 AVSS 73 N.C. 72 N.C. 71 N.C. 70 N.C. 69 AVDD 68 AVSS 67 N.C. 66 AVDD 65 AVSS 64 N.C. 63 AVSS 62 AVDD 61 TPA 60 TPB 59 TPA 58 TPB 57 AVSS 56 AVDD 55 TPBIAS 54 AVSS 53 AVDD 52 ROI 51 N.C.
AD5 18 AD4 19 AD3 20 AD2 21 AD1 22 D0 VDD VSS 23 24 25
WR (DS) 26
27 28 29 30 31 32 33 34 35 RD (R/W) VDD VSS CS A5 A4 A3 A2 A1
(FPT-100P-M05)
N.C. DREQ DACK VDD VSS X0 X1 TESTP AVSS AVDD VCOIN CHPO ROP AVSS AVDD
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3
MB86615
2. FBGA-120
13 N.C.
12 AVDD
11 AVSS
10 VCOIN
9 TESTP
8 XO
7 DACK
6 N.C.
5 A3
4 A5
3 VDD
2 N.C. RD (R/W) N.C.
1 WR (DS) VSS N
N.C.
ROI
N.C. TPBIAS TPB N.C. AVSS AVSS N.C. N.C. N.C. TEST3 VSS
CHPO
AVSS
X1
VDD
DREQ
A2
A4
VSS
M
AVDD
AVSS
ROP
AVDD
N.C.
VSS
N.C.
A1
N.C.
CS
VDD
L
AVDD TPA TPA N.C. AVDD AVSS N.C. N.C. AVDD
AVSS TPB AVDD N.C. N.C. AVDD N.C. AVSS TEST2
D0 AD3 D6 TOP VIEW VSS N.C. D11 D13 ID7 N.C. ID4 ID5 ID1 ID2 ID3 VSS ID0 IDIR ICLK IV N.C. TEST5 FP ALE N.C. MODE 0
AD1 AD4 N.C. VDD D9 D12 D14 VSS INT MODE 1
AD2 AD5 D7 D8 D10 N.C. D15 VDD N.C.
K J I H G E D C B
TEST1
N.C.
VDD
TEST4
ID6
N.C.
VDD
ILWRE
ICRCE
RESET
A
1 pin
4
MB86615
s PIN LIST
1. LQFP-100
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 I/O ID I O -- -- ID I IU/O ID/O IU/O ID/O IU/O ID/O IU/O ID/O IU/O ID/O IU/O ID/O IU/O ID/O IU/O ID/O -- -- IU/O ID/O IU/O ID/O IU/O ID/O IU/O ID/O IU/O ID/O IU/O ID/O IU/O ID/O IU/O ID/O -- -- ID I ID I -- -- ID I ID I ID I ID I -- I -- I Pin Name RESET INT VDD VSS ALE D15 D14 D13 D12 D11 D10 D9 D8 VDD VSS D7 D6 AD5 AD4 AD3 AD2 AD1 D0 VDD VSS WR (XDS) WR (DS) RD (R/W) VDD VSS CS A5 A4 A3 VDD A2 VSS A1 NO. 36 34 37 35 38 36 39 37 40 38 41 39 42 40 43 41 44 42 45 43 46 44 47 45 48 46 49 47 50 48 51 49 52 50 53 51 54 52 55 53 56 54 57 55 58 56 59 57 60 58 61 59 62 60 63 61 64 62 65 63 66 64 67 65 68 66 69 57 70 58 I/O -- ID ID O IU I -- O -- O I/O -- -- I I/O O -- I -- -- I -- O O I -- O -- O -- -- O -- -- O -- O -- -- O I/O -- I/O -- I/O I/O I/O -- I/O -- -- -- -- O -- -- -- I/O -- Pin Name N.C. A2 DREQ A1 PMODE DACK CTR VDD OCLK VSS VDD X0 VSS X1 TESTP X0 AVSS X1 TESTP AVDD VCOIN AVSS CHPO AVDD VCOIN ROP CHPO AVSS AVDD ROP AVSS N.C. AVDD ROI AVDD N.C. AVSS RO1 TPBIAS AVDD AVDD AVSS TAPBIAS1 AVSS AVDD TPB AVSS TPA TPB1 TPB TPA1 TPA TPB1 AVDD TPA1 AVSS RO0 N.C. AVDD AVSS AVDD AVSS RO0 N.C. AVDD AVSS AVDD TPB1 N.C.
(Continued)
5
MB86615
(Continued)
NO. 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 I/O -- -- -- -- -- IU/O IU/O -- -- IU/O IU/O I/O I/O I/O I/O Pin Name N.C. N.C. N.C. AVSS AVDD TEST1 TEST2 VDD VSS TEST3 TEST4 ID7 ID6 ID5 ID4 NO. 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O I/O I/O I/O I/O -- -- I I O I O I/O O I I Pin Name ID3 ID2 ID1 ID0 VSS VDD ICLK IDIR ILWRE IV ICRCE FP TEST5 MODE0 MODE1
6
MB86615
2. FBGA-120
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Ball No. A1 B1 B2 C1 C2 C3 D1 D2 D3 E1 E2 E3 F1 F2 F3 G1 G2 G3 H1 H2 H3 J1 J2 J3 K1 K2 K3 L1 L2 M1 N1 N2 M2 N3 M3 L3 I/O I -- O -- -- I IU/O IU/O IU/O -- IU/O IU/O IU/O IU/O -- IU/O -- -- IU/O -- IU/O IU/O IU/O IU/O IU/O IU/O IU/O -- -- -- I -- I -- -- I Pin Name RESET N.C. INT VDD VSS ALE D15 D14 D13 N.C. D12 D11 D10 D9 N.C. D8 VDD VSS D7 N.C. D6 AD5 AD4 AD3 AD2 AD1 D0 VDD N.C. VSS WR (DS) N.C. RD (R/W) VDD VSS CS Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ball No. N4 M4 L4 N5 M5 L5 N6 M6 L6 N7 M7 L7 N8 M8 L8 N9 M9 L9 N10 M10 L10 N11 M11 N12 N13 M13 M12 L13 L12 L11 K13 K12 K11 J13 J12 J11 I/O I I -- I I I -- O -- I -- -- I/O I -- O -- -- I O O -- -- -- -- -- O -- -- O -- -- I/O I/O I/O -- Pin Name A5 A4 N.C. A3 A2 A1 N.C. DREQ N.C. DACK VDD VSS X0 X1 N.C. TESTP AVSS AVDD VCOIN CHPO ROP AVSS N.C. AVDD N.C. N.C. ROI AVDD AVSS TPBIAS AVDD AVSS TPB TPA TPB N.C. Pin No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Ball No. H13 H12 H11 G13 G12 G11 F13 F12 F11 E13 E12 E11 D13 D12 D11 C13 C12 B13 A13 A12 B12 A11 B11 C11 A10 B10 C10 A9 B9 C9 A8 B8 C8 A7 B7 C7 I/O I/O -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IU/O -- IU/O -- -- IU/O IU/O -- I/O I/O I/O I/O I/O I/O I/O -- I/O -- Pin Name TPA AVDD AVSS N.C. N.C. AVSS AVDD N.C. N.C. AVSS AVDD N.C. N.C. N.C. N.C. N.C. AVSS AVDD TEST1 N.C. TEST2 VDD VSS TEST3 TEST4 N.C. ID7 ID6 ID5 ID4 ID3 ID2 ID1 N.C. ID0 VSS
(Continued)
7
MB86615
(Continued)
Pin No. 109 110 111 112 Ball No. A6 B6 C6 A5 I/O -- I I O Pin Name VDD ICLK IDIR ILWRE Pin No. 113 114 115 116 Ball No. B5 C5 A4 B4 I/O -- I O I/O Pin Name N.C. IV ICRCE FP Pin No. 117 118 119 120 Ball No. C4 A3 B3 A2 I/O O I -- I Pin Name TEST5 MODE0 N.C. MODE1
8
MB86615
s PIN DESCRIPTION
1. 1394 Interface
Pin name TPA TPA TPB TPB TPBIAS ROI I/O I/O I/O I/O I/O O O Function 1394 Cable port TPA positive signal I/O pin 1394 Cable port TPA negative signal I/O pin 1394 Cable port TPB positive signal I/O pin 1394 Cable port TPB negative signal I/O pin 1394 Cable port common voltage reference voltage output pin Connect to GND through 4.7 k resistance
2. Isochronous-data Interface
Pin name ICLK I/O I Function Isochronous data interface CLK signal input pin (4 MHz to 16 MHz). Isochronous transfer transmission/reception switching signal input pin. 0 input: The device clears the ISO-FIFO buffer and enters the transmission mode. The device asserts the ILWRE signal and starts transmission after receiving one packet of data according to the "data-length" setting (bank 0: 10h). 1 input: The device clears the ISO-FIFO buffer and enters the reception mode. If any packet being transmitted exists, the device enters the reception mode after completing transmission of the packet. The ILWRE signal is asserted upon reception of one packet. Note: The IDIR signal should normally be left at "1" and switched to "0" only for transmission. ISO-FIFO access enable signal output pin. Transmission mode: The signal is asserted when the FIFO buffer is not full. The signal is negated when the FIFO buffer becomes full. When it is negated, data is accepted only up to the rising edge of the next ICLK signal. When a bus reset is detected, the signal is negated after accepting data of up to the packet boundary. After the bus reset, the signal is asserted again upon completion of transmission of one source packet remaining in the FIFO buffer. Reception mode: The signal is asserted upon completion of one packet of data. The signal is negated once when one packet of data is read from the FIFO buffer and asserted back if the FIFO buffer still contains any packet of data which has been received completely. Isochronous transfer data input/output bits. (MSB is ID7, LSB is ID0) ID7 to ID0 enable signal input pin Transmission mode: While the IV signal is active, data from the ID7 to ID0 pins is loaded into the ISO-FIFO buffer at the rising edge of the ICLK signal. Reception mode: While the signal becomes active, the device starts sending data from the ISO-FIFO buffer to the ID7 to ID0 pins. Data is then switched at the rising edge of the ICLK signal.
IDIR
I
ILWRE
O
ID7 to ID0
I/O
IV
I
(Continued)
9
MB86615
(Continued)
Pin name ICREC I/O O Function This pin outputs a signal indicating that data sent in the reception mode is data in a packet from which a data-CRC error has been detected. Time stamp trigger signal I/O pin. Transmission mode: This pin inputs the time stamp trigger signal. The value in the internal cycle timer register is fetched upon detection of the falling edge of the FP signal. Reception mode: Time stamp match detection signal output pin.
FP
I/O
3. System Interface
Pin name CS A5 to A1 D15 to D6, D0 AD5 to AD1 I/O I I I/O I/O Function Input pin for signals used by the MPU to select the MB86615 as an I/O device. Address input pins for internal register selection. Valid only in non-multiplexed mode. If multiplexed mode is selected these pins should be fixed at `0'. 16-bit data bus input/output pins (MSB is D15, LSB is D0). 16-bit data bus input/output pins (MSB is AD5, LSB is AD1). Used for address input signals when multiplexed mode is selected. 80-series mode: Read strobe signal input pin, used to output data from the MB86615 to the data bus. 68-series mode: Control signal input pin, used for data input/output operations to the MB86615. 80-series mode: Write strobe signal input pin, used to input data from the data bus to the MB86615. 68-series mode: DS signal input pin, output when data bus is enabled. ALE signal input pin, for signal output when addresses are enabled in multiplexed mode. In non-multiplexed mode, this signal should be fixed at `0'. This pin outputs the DMA transfer request signal to the DMAC for asynchronous transfer in DMA mode. The signal requests DMA transfer between the device and memory. This pin inputs the DMA enable signal from the DMAC for asynchronous transfer in DMA mode. Interrupt output pin.
RD (R/W)
I
WR (DS) ALE DREQ DACK INT
I I O I O
10
MB86615
4. Other
Pin name X0 X1 VCOIN CHPO ROP RESET MODE0 MODE1 TESTP TEST1 to TEST4 TEST5 AVDD AVSS VDD VSS N.C. I/O I/O I I O O I I I O IU/O O -- -- -- -- -- Function External crystal connection pins for oscillator circuits. VCO input pin for internal PLL. Charge pump output pin for internal PLL. Connect to GND through 4.7 k resistance. Reset signal input pin. The device enters the forced sleep mode automatically upon detection of the RESET signal asserted. Input `0' for 80-series mode. Input `1' for 68-series mode. Input `0' for non-multiplexed mode. Input `1' for multiplexed mode. Test pin. Do not connect. Test pin. Do not connect. Test pin. Do not connect. Analog power supply Analog ground Digital power supply Digital ground Unused pin. Do not connect.
11
MB86615
s BLOCK DIAGRAM
IDIR ICLK ISO sending/receiving FIFO (1kB) ILWRE Isochronous interface ID7 to ID0 IV ISO sending packet processing TPA 1394 interface TPA TPB TPB TPBIAS
ICRCE FP
ISO receiving packet processing
LINK layer control circuit
PHY layer control circuit
CS A5 to A1 System & asynchronous interface
ASYNC send-only FIFO (128 byte)
ASYNC sending packet processing
D15 to D6, D0 AD5 to AD1 RD (R/W) WR (DS) ALE INT DREQ DACK
ASYNC receive-only FIFO (128 byte)
ASYNC receiving packet processing
Cycle master
Transaction control circuit block
Dedicated transaction control circuit block
PLL circuit
Register block
CSR
12
MB86615
s BLOCK DESCRIPTIONS
* PHY Layer Control Circuit This block contains the IEEE 1394 physical layer control circuits. Both asynchronous transfer and isochronous transfer in a cable environment are supported. The transfer speed is 100 Mbit/sec. One analog transceiver/receiver ports are built-in. This block provides bus status monitoring initialization operation after a bus reset is applied, as well as arbitration and encoding/decoding functions for data sending and receiving. * LINK Layer Control Circuit This block controls the generation and transfer of IEEE 1394 standard packets. 32-bit CRC generation and checking is performed for packet headers and data. A 32-bit cycle timer register is built-in to provide cycle master functions. * Sending/Receiving FIFO Contains built-in 1-byte FIFO areas, used for isochronous transfer for both sending and receiving. Contains independent sending and receiving 128-byte FIFO areas for asynchronous transfer. * Packet Processing Sending: Performs packetizing of headers, data and CRC. Automatically generates and attaches CRC. Receiving: Separates 1394 packet headers and data, strips CRC. * Transaction Control Circuit Block This block controls the 1394 bus protocol based on a variety of instructions. * Dedicated Transaction Circuit Block This block packetizes data from the isochronous interface for DVC and rebuilds received data for the isochronous interface in conjunction with the packet processing block. * Register Block This block contains various device control registers, as well as registers for setting parameters required for transfer, DVC registers and CSR. The built-in CSR provides isochronous resource manager functions. * PLL Circuit This block uses the reference clock signal generated by the crystal oscillator circuit to create internal operating clock and transfer clock signals. Reference oscillator frequency: 8.192 MHz.
13
MB86615
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage*1 Input voltage*1 Output voltage*1 Strage temperature Operating temperature* Output current* Overshoot*
4 4 3 2
Symbol VDD VI VO Tst Top IO -- --
Rating Min. VSS - 0.5 VSS - 0.5 VSS - 0.5 -55 -40 -14 -- -- Max. 4.0 VDD + 0.5 VDD + 0.5 +125 +85 +14 VDD + 1.0 VSS - 1.0
Unit V V V C C mA V V
Undershoot* *1: *2: *3: *4:
Voltage values are based on Vss = 0 V. Not warranted for continuous operation. Normal output current flow (Minimum at Vo = 0 V, maximum at Vo = VDD). 50 ns or less.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage* "H" level input voltage "L" level input voltage Differential input voltage (for data transfer) Differential input voltage (for arbitration) Common mode input voltage Receiving input jitter Receiving input skew Output current Operating temperature * : Voltage values are based on Vss = 0 V. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 14 CMOS input CMOS input Cable input Cable input Cable input Cable input Cable input CMOS output TPBIAS Symbol VDD VIH VIL VID VIDA VCM -- -- IOH/IOL Iot Ta Value Min. 3.0 VDD x 0.65 VSS 142 173 1.165 -- -- -4 -2 0 Max. 3.6 VDD VDD x 0.25 260 260 2.515 1.08 0.8 +4 +10 +70 Unit V V V mV mV V ns ns mA mA C
MB86615
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics 1.1 1394 Interface Driver
Parameter Differential output voltage Common phase current Off state voltage TPBIAS output voltage Symbol VOD ICM VOFF VO (VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70C) Value Conditions Unit Min. Max. R1 = 56 Driver enabled Driver disabled -- 172 -0.81 -- 1.665 265 0.44 20 2.015 mV mA mV V
1.2 1394 Interface - Comparator
Parameter Common phase input current Arbitration comparator "H" level detection offset Arbitration comparator "Z" level detection offset Arbitration comparator "L" level detection offset Port status comparator disconnection detect voltage Port status comparator connection detect voltage Symbol IIC VSCH VSCZ VSCL VSD VSC (VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70C) Value Conditions Unit Min. Max. Driver disabled Driver disabled Driver disabled Driver disabled Driver disabled Driver disabled -20 168 -30 -- -- 1.0 20 -- 30 -168 0.6 -- A mV mV mV V V
15
MB86615
1.3 System Interface, etc
(VDD = 3 to 3.6 V , VSS = 0 V, Ta = 0 to +70C) Value Unit Min. Typ. Max. VDD x 0.65 VSS VDD - 0.5 VSS -5 VI = 0V to VDD VIH = 0 1394 port connected 1394 port non connected Forced sleep -5 25 -- -- -- -- -- -- -- -- -- 50 -- -- -- VDD VDD x 0.25 VDD 0.4 5 5 200 200 180 30 V V V V A A k mA mA mA
Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input pins Input leak current Input pull-up resistance 3-state pin input
Symbol VIH VIL VOH VOL ILI ILZ Rp IDD1
Conditions CMOS CMOS IOH = -4 mA IOL = +4 mA
Power supply current
IDD0 IDDS
16
MB86615
2. AC Characteristics 2.1 1394 Driver
Parameter Sending jitter Sending skew Sending rise time* Conditions Sending fall time* CL = 10 pF. RL = 56 * : 10 to 90% value. Symbol tJT tSK tDR tDF Value Min. -- -- -- -- Max. 0.8 0.8 3.2 3.2 Unit ns ns ns ns
2.2 System Clock
Parameter Clock frequency Clock cycle time Clock pulse width Clock rise time Clock fall time High Low Symbol fC tCLF tCLCH tCLCL tCR tCF Value Min. 8.191992 -- 50 50 -- -- Typ. 8.192 1/fc -- -- -- -- Max. 8.192008 -- -- -- 5 5 Unit MHz ns ns ns ns ns
tCLCH tCF 0. 65 VDD 0. 25 VDD
tCLF tCR
CLK
tCLCL
17
MB86615
2.3 System Reset
Parameter Reset (RESET) "L" level pulse width Symbol tWRSL Value Min. 4 tclf Max. -- Unit ns
tWRSL
RESET
18
MB86615
2.4 MPU Interface
(1) 68-Series Register Write Operation (multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time R/W setup time R/W hold time ALE "H" level pulse width ALE fall to DS fall time DS "L" level pulse width Data setup time Data hold time DS rise to ALE rise time Symbol tAWSM tAWHM tCWSM tCWHM tRWSM tRWHM tALE tDWD tDSM tDWSM tDWHM tLWD Value Min. 10 10 20 10 20 10 15 15 40 10 0 20 Max. -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
tCWSM
tCWHM
CS
tRWSM tRWHM
R/W
tALE tDWD tLWD
ALE
tDSM
DS
tAWSM tAWHM tDWSM Data tDWHM
D15 to D6, D0 AD5 to AD1
Address
19
MB86615
(2) 68-System Register Read Operation (multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time R/W setup time R/W hold time ALE "H" level pulse width ALE fall to DS fall time DS "L" level pulse width Data output definition time Data output disabled time DS rise to ALE rise time Symbol tARSM tARHM tCRSM tCRHM tRWSM tRWH tALE tDRD tDSM tRLDM tRHDM tLRD Value Min. 10 10 20 10 20 10 15 15 40 -- 5 20 Max. -- -- -- -- -- -- -- -- -- 40 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
tCRSM
tCRHM
CS
tRWSM
tRWH
R/W
tLRD
tALE
tDRD
ALE
tDSM
DS
tARSM
tARHM
tRLDM
tRHDM Defined data
D15 to D6, D0 AD5 to AD1
Address
20
MB86615
(3) 68-Series Register Write Operation (non-multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time R/W setup time R/W hold time DS "L" level pulse width Data setup time Data hold time Symbol tAWS tAWH tCWS tCWH tRWS tRWH tDS tDWS tDWH Value Min. 10 20 20 10 20 10 40 40 0 Max. -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns
tAWS
tAWH
A5 to A0
tCWS tCWH
CS
tRWS
tRWH
R/W
tDS
DS
tDWS tDWH Data
D15 to D6, D0 AD5 to AD1
21
MB86615
(4) 68-Series Register Read Operation (non-multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time R/W setup time R/W hold time DS "L" level pulse width Data output definition time Data output disabled time Symbol tARS tARH tCRS tCRH tRWS tRWH tDS tRLD tRHD Value Min. 10 20 20 10 20 10 40 -- 5 Max. -- -- -- -- -- -- -- 40 -- Unit ns ns ns ns ns ns ns ns ns
tARS
tARH Address
A5 to A0
tCRS
tCRH
CS
tRWS
tRWH
R/W
tDS
DS
tRLD tRHD Defined data
D15 to D6, D0 AD5 to AD1
22
MB86615
(5) 80-Series Register Write Operation (multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time ALE "H" level pulse width ALE fall to WR fall time WR "L" level pulse width Data setup time Data hold time WR rise to ALE rise time Symbol tAWSM tAWHM tCWSM tCWHM tALE tDWD tWRM tDWSM tDWHM tLWD Value Min. 10 10 20 10 15 15 40 40 0 20 Max. -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns
tCWSM
tCWHM
CS
tALE
tDWD
tLWD
ALE
tWRM
WR
tAWSM
tAWHM
tDWSM Data
tDWHM
D15 to D6, D0 AD5 to AD1
Address
23
MB86615
(6) 80-Series Register Read Operation (multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time ALE "H" level pulse width ALE fall to RD fall time RD "L" level pulse width Data output definition time Data output disabled time RD rise to ALE rise time Symbol tARSM tARAHM tCRSM tCRHM tALE tDRD tRDM tRLDM tRHDM tLRD Value Min. 10 10 20 10 15 15 40 -- 5 20 Max. -- -- -- -- -- -- -- 40 -- -- Unit ns ns ns ns ns ns ns ns ns ns
tCRSM
tCRHM
CS
tALE
tDRD
tLRD
ALE
tRDM
RD
tRHDM Defined data
tARSM
tARAHM
tRLDM
D15 to D6, D0 AD5 to AD1
Address
24
MB86615
(7) 80-Series Register Write Operation (non-multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time WR "L" level pulse width Data setup time Data hold time Symbol tAWS tAWH tCWS tCWH tWR tDWS tDWH Value Min. 10 20 20 10 40 40 0 Max. -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
tAWS
tAWH Address
A5 to A0
tCWS
tCWH
CS
tWR
WR
tDWS tDWH Data
D15 to D6, D0 AD5 to AD1
25
MB86615
(8) 80-Series Register Read Operation (non-multiplexed) Parameter Address setup time Address hold time CS setup time CS hold time RD "L" level pulse width Data output definition time Data output disabled time Symbol tARS tARH tCRS tCRH tRD tRLD tRHD Value Min. 10 20 20 10 40 -- 5 Max. -- -- -- -- -- 40 -- Unit ns ns ns ns ns ns ns
tARS
tARH Address
A5 to 0
tCRS
tCRH
CS
tRD
RD
tRLD tRHD Defined data
D15 to D6, D0 AD5 to AD1
(9) INT Signal Operation Parameter Interrupt read operation to INT signal negate Symbol tINTD Value Min. 100 Max. -- Unit ns
RD, DS
tINTD
INT
Note: This specification applies only to reading of the last data from the interrupt holding register. For other read-related specifications, conform to the respective specifications for individual modes. 26
MB86615
2.5 DMA Access
(1) 68-Series DMA Write Operation Parameter DREQ "H" to DACK "L"
DS "H" to DREQ "L" DACK setup time DACK hold time
Symbol tDHAL tDHDL tDAWS tDAWH tDRWS tDRWH tDDS tDDSH tDDWS tDDWH
Value Min. 0 -- 20 0 20 10 40 30 30 0 Max. -- 30 -- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns
R/W setup time R/W hold time DS "L" level pulse width DS "H" level pulse width Input data setup time Input data hold time
tDHAL
tDHDL
DREQ
tDAWS tDAWH
DACK
tDRWS tDRWH
R/W
tDDS tDDSH
DS
tDDWS tDDWH Data
D15 to D6, D0 AD5 to AD1
Data
27
MB86615
(2) 68-Series DMA Read Operation Parameter DREQ "H" to DACK "L"
DS "H" to DREQ "L" DACK setup time DACK hold time
Symbol tDHAL tDHDL tDARS tDARH tDRWS tDRWH tDDS tDDSH tDRLD tDRHD
Value Min. 0 -- 20 0 20 10 40 30 -- 5 Max. -- 30 -- -- -- -- -- -- 40 --
Unit ns ns ns ns ns ns ns ns ns ns
R/W setup time R/W hold time DS "L" level pulse width DS "H" level pulse width Data output definition time Data output disabled time
tDHAL
tDHDL
DREQ
tDARS tDARH
DACK
tDRWS tDRWH
R/W
tDDS tDDSH
DS
tDRLD tDRHD Defined data Defined data
D15 to D6, D0 AD5 to AD1
28
MB86615
(3) 80-Series DMA Write Operation Parameter DREQ "H" to DACK "L" WR "H" to DREQ "L" DACK setup time DACK hold time WR "L" level pulse width WR "H" level pulse width Input data setup time Input data hold time Symbol tDHAL tDHDL tDAWS tDAWH tDWR tDWRH tDDWS tDDWH Value Min. 0 -- 20 0 40 30 30 0 Max. -- 30 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns
tDHAL
tDHDL
DREQ
tDAWS tDAWH
DACK
tDWR
tDWRH
WR
tDDWS tDDWH Data
D15 to D6, D0 AD5 to AD1
Data
29
MB86615
(4) 80-Series DMA Read Operation Parameter DREQ "H" to DACK "L"
RD "H" to DREQ "L" DACK setup time DACK hold time
Symbol tDHAL tDHDL tDARS tDARH tDRD tDRDH tDRLD tDRHD
Value Min. 0 -- 20 0 40 30 -- 5 Max. -- 30 -- -- -- -- 40 --
Unit ns ns ns ns ns ns ns ns
RD "L" level pulse width RD "H" level pulse width Data output definition time Data output disabled time
tDHAL
tDHDL
DREQ
tDARS tDARH
DACK
tDRD
tDRDH
RD
tDRLD tDRHD Defined data Defined data
D15 to D6, D0 AD5 to AD1
30
MB86615
2.6 Isochronous Interface 2.6.1 ICLK
Parameter Clock frequency Clock cycle time Clock "H" level pulse width Clock "L" level pulse width Clock rise time Clock fall time Symbol -- tICLK tICLH tICLL tICR tICF Value Min. 4 62.5 20 20 -- -- Max. 16 250 -- -- 7 7 Unit MHz ns ns ns ns ns
tICLH tICF 0. 65 VDD 0. 25 VDD
tICLK tICR
ICLK
tICLL
31
MB86615
2.6.2 Sending Operation
(1) Start Sending Operation Parameter IDIR fall to ILWRE fall time ICLK rise to ILWRE fall time ILWRE fall to IV fall time IV setup time Data setup time Data hold time Symbol tSDIR tSIDIR tILIV tSIV tSD tHD Value Min. -- -- 0 40 20 0 Max. tICLK + 125 40 -- -- -- -- Unit ns ns ns ns ns ns
ICLK
IDIR
tSIDIR tSDIR tILIV
ILWRE
tSIV
IV
tSD tHD
ID7 to ID0
1
2
3
32
MB86615
(2) End Sending Operation Parameter IV rise to IDIR rise time IDIR rise to ILWRE rise time ICLK rise to ILWRE rise time IDIR rise to IDIR fall time Symbol tHDIR tDWR tSWDIR tDIRH Value Min. 0 -- -- 250 Max. -- 1 tICLK + 40 40 -- Unit ns ns ns s
ICLK
IDIR
tSWDIR tDWR
ILWRE
tHDIR tDIRH
IV
ID7 to ID0
N-1
N
N+1
33
MB86615
(3) IV Temporary Negation in Sending Operation Parameter IV hold time Date setup time Data hold time Symbol tHIV tSD tHD Value Min. 0 20 0 Max. tICLK - 40 -- -- Unit ns ns ns
ICLK
IDIR
ILWRE
tHIV
IV
tSD tHD N N+1
ID7 to ID0
N-1
34
MB86615
(4) Negating ILWRE during Transmission (with a bus reset detected or the FIFO buffer full) Parameter ICLK rise to ILWRE rise time ILWRE rise to IV rise time ICLK rise to ILWRE fall time Symbol tHWRL tREMIV tHWRH Value Min. -- tICLK -- Max. 40 2 tICLK - 40 40 Unit ns ns ns
ICLK
IDIR
tHWRL
tHWRH
ILWRE
tREMIV
IV
ID7 to ID0
valid
valid
valid
ignore
Note: The ILWRE signal is negated to stop writing data to be transmitted in either of the following cases in the transmission mode (1) When the ISO transmission/reception FIFO buffer becomes full (The ILWRE signal is negated in synchronization with the last ICLK signal generated before the FIFO buffer becomes full. Note, however, that this condition does not negate the ILWRE signal if the point-rcc bit (bit 7) in the ISO-FIFO control register (address 0Eh) has been set to "1." (2) When a bus reset is detected (The ILWRE signal is negated in synchronization with the last ICLK signal generated before the FIFO buffer loads one packet of data after detection of the bus reset.) The ILWRE signal is asserted back when transmission of one packet of data to the 1394 bus is completed.
35
MB86615
(5) Switch to Transmission from Reception in Process Parameter IDIR fall to ILWRE rise time IDIR fall to ILWRE fall time Symbol tDLWRH tDLWRL Value Min. -- -- Max. tICLK + 40 2 tICLK + 40 Unit ns ns
ICLK
IDIR
tDLWRL tDLWRH
ILWRE
(6) FP Input Timing Parameter FP "L" level pulse width FP "H" level pulse width FP "H" detection to CTR value load Symbol tFPL tFPH -- Value Min. 100 125 80 Max. -- -- 150 Unit ns s ns
tFPL
tFPH
FP
36
MB86615
2.6.3 Receiving Operation
(1) Start Receiving Operation Parameter ICLK rise to ILWRE fall IV setup time Data output definition time Data output disable time IV fall to ICRCE fall time* Symbol tWREH tSIV tDZ tD tERRL Value Min. -- 40 -- 10 -- Max. 40 -- 40 40 40 Unit ns ns ns ns ns
* : The ICRCE signal is output when a CRC error is detected in receiving data.
ICLK
IDIR
tWREH
ILWRE
tSIV
IV
tDZ tD
ID7 to ID0
Hi - Z tERRL
1
2
3
ICRCE
37
MB86615
(2) End Receiving Operation Parameter ICLK rise to ILWRE rise Data output disable time ILWRE negate time*1 IV rise to ICRCE rise time*2 Symbol tWREL tZD tWREH tERRH Value Min. -- 0 6 tICLK -- Max. 40 50 -- 40 Unit ns ns ns ns
*1: This device negates the ILWRE signal upon completion of reading each packet of data. *2: The ICRCE signal is asserted only when a CRC error is detected in data received.
ICLK
IDIR
tWREL tWREH
ILWRE
IV
tZD
ID7 to ID0
N-2
N-1
N tERRH
Hi - Z
ICRCE
38
MB86615
(3) IV Temporary Negation in Receiving Operation Parameter IV rise to ICLK rise IV rise to ICRCE rise time IV fall to ICRCE fall time Symbol tHIV tERRH tERRL Value Min. 40 -- -- Max. -- 40 40 Unit ns ns ns
ICLK
IDIR
ILWRE
tHIV
IV
ID7 to ID0
N-3
N-2 tERRH
Hi - Z tERRL
N-1
ICRCE
39
MB86615
(4) FP Signal Output Parameter IDIR fall to FP output enable FP "L" level pulse width Time stamp match detect to FP output Symbol tZFP tFPW -- Value Min. -- 600 -- Max. 40 730 40 Unit ns ns ns
IDIR
tZFP Hi - Z tFPW
FP
40
MB86615
2.6.4 Clearing the ISO Transmission/Reception FIFO Buffer Using the fifo-clr Bit
The ISO transmission/reception FIFO buffer is cleared by setting the fifo-clr bit (bit 4) in the ISO-FIFO control register (address 0Eh) to "1." Given below is a timing chart for the isochronous interface when the FIFO buffer is cleared. Note that this FIFO buffer clear function is available only when the point-rec bit (bit 7) or length-chk bit (bit 6) in the ISO-FIFO control register has been set to "1."
Parameter IV rise to ILWRE rise ILWRE negate time
Symbol tCLR tWREH
Value Min. -- -- Max. 4 tICLK 7 tICLK
Unit ns ns
tCLR
tWREH
ILWRE
IV
* : The ISO transmission/reception FIFO buffer is cleared while the ILWRE signal is negated.
41
MB86615
s INTERNAL REGISTERS
The MB86615 internal registers have 3-bank construction, with 16-bit access to all registers. Bank 0 contains registers necessary for IEEE 1394 settings and transfer, bank 1 contains registers necessary for AV/C (DVC) operation, and bank 2 contains CSR's. In addition each bank has registers used in common for MB86615 device control.
1. Bank Common Registers
The following registers can be accessed in any bank from bank 0 to bank 2. Address HEX 00 02 04 06 08 0A 0C 0E 3E A5 0 0 0 0 0 0 0 0 1 A4 0 0 0 0 0 0 0 0 1 A3 0 0 0 0 1 1 1 1 1 A2 0 0 1 1 0 0 1 1 1 A1 0 1 0 1 0 1 0 1 1 Write operation mode-control register (reserved) instruction fetch register interrupt mask register (reserved) ASYNC data port (sending) mode-control-2 register ISO-FIFO control register bank select register Read operation flag & status register interrupt code register Receiving acknowledge display register ASYNC data port (receiving)
42
MB86615
2. Bank 0 Registers
Bank 0 contains the registers required for 1394 settings and transfers. Access to this bank is enabled by writing `0000h' to the bank select register (3Eh). Address HEX 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C A5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Write operation Sending ISO PKT header setting register (high) Sending ISO PKT header setting register (low) Sending ASYNC des ID setting register Sending ASYNC PKT param setting register Sending ASYNC data length setting register Sending ASYNC ex tcode setting register Sending ASYNC source ID setting register Sending ASYNC resp param setting register Sending ASYNC des offset setting register (high) Sending ASYNC des offset setting register (middle) Sending ASYNC des offset setting register (low) (reserved) (reserved) (reserved) (reserved) (reserved) state clear setting register Self ID PKT param setting register Receiving ISO-channel setting register (0, 1) Receiving ISO-channel setting register (2, 3) (reserved) (reserved) (reserved) Read operation Receiving ISO PKT header display register (high) Receiving ISO PKT header display register (low) Receiving ASYNC des ID setting register Receiving ASYNC PKT param display register Receiving ASYNC data length display register Receiving ASYNC ex tcode display register Receiving ASYNC source ID display register Receiving ASYNC resp param display register Receiving ASYNC des offset display register (high) Receiving ASYNC des offset display register (middle) Receiving ASYNC des offset display register (low) PHY ID display register NODE config display register PORT config display register root ID display register ISO resource manager ID display register cycle timer monitor display register (high) cycle timer monitor display register (low)
43
MB86615
3. Bank 1 Registers
Bank 1 contains the registers required for AV/C (DVC) protocols. Access to this bank is enabled by writing `0001h' to the bank select register (3Eh). Address HEX 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C A5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Write operation Sending time stamp offset setting register Receiving time stamp offset setting register Sending CIP header DBS setting register (reserved) Sending CIP header FMT setting register (reserved) OMPR (high) OMPR (low) OPCR0 (high) OPCR0 (low) (reserved) (reserved) (reserved) (reserved) IMPR (high) IMPR (low) IPCR0 (high) IPCR0 (low) (reserved) (reserved) (reserved) (reserved) set-PCR & FP-timeout setting register Read operation Receiving CIP header display register (highest) Receiving CIP header display register (high) Receiving CIP header display register (low) Receiving CIP header display register (lowest)
44
MB86615
4. Bank 2 Registers
Bank 2 contains CSR's required for Isochronous resource manager. Access to this bank is enabled by writing `0002h' to the bank select register (3Eh). Address HEX 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C A5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A4 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 A2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Write operation bus manager ID register (high) bus manager ID register (low) bandwidth available register (high) bandwidth available register (low) channels available high register (high) channels available high register (low) channels available low register (high) channels available low register (low) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) (reserved) Read operation
45
MB86615
s ORDERING INFORMATION
Partnumber MB86615PFV MB86615PBT Package 100-pin plastic LQFP (FPT-100P-M05) 120-pin plastic FBGA (BGA-120P-M01) Remarks
46
MB86615
s PACKAGE DIMENSIONS
100-pin plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
14.000.10(.551.004)SQ
51
1.50 -0.10 (Mounting height) +.008 .059 -.004
+0.20
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05
"A" 0.50(.0197)TYP 0.18 -0.03 +.003 .007 -.001
+0.08
0.40(.016)MAX 0.127 -0.02 +.002 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
120-pin plastic FBGA (BGA-120P-M01)
12.000.10(.472.004)SQ 1.25 -0.10 .049 -.004 (Mounting height) 0.380.10(.015.004) (Stand off)
+0.20 +.008
9.60(.378)REF 0.80(.031)TYP
13 12 11 10 9 8 7 6 0.10(.004) 5 4 INDEX 3 2 1 NMLKJHGFEDCBA C0.80(.031) 120-O0.450.10 (120-O.018.004) 0.08(.003)
M
C
1998 FUJITSU LIMITED B120001S-1C-1
Dimensions in mm (inches)
47
MB86615
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9902 (c) FUJITSU LIMITED Printed in Japan
48

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